The present invention relates generally to a semiconductor device and a method for producing the same. More specifically, the invention relates to a method for producing a semiconductor device, such a bipolar transistor, which has a small parasitic capacity, a small parasitic resistance and a high performance, and a semiconductor device produced by this method.
In recent years, there is proposed a device capable of realizing accelerating and high integration by forming a shallow junction in a device active region, such as a base layer of a bipolar transistor element, and source/drain and channel regions of a CMOSFET element, using a low temperature epitaxial growth method, and such a device is in the process of practical use. Referring to FIG. 1A through 1H, a conventional bipolar transistor as an example of a semiconductor device having such a structure, and a method for producing the same will be described below.
As shown in FIG. 1H(a), a semiconductor substrate 1 comprises a p-type silicon substrate 11, an n.sup.+ -impurity diffusion region 12 formed by allowing an n-type impurity to diffuse and grow on one side of the silicon substrate 11 at a high concentration, and an n.sup.- -epitaxial growth layer 13 formed by allowing an n-type impurity to epitamially grow on the impurity diffusion region 12 at a low concentration. A trench is formed in the major surface of such a semiconductor substrate 1, i.e., in a surface of the epitaxial growth layer 13, and an insulating material, such as silicon dioxide (SiO.sub.2), is filled therein to form an element isolating region 10. The surface of an element forming region, which is a region surrounded by the element isolating region 13 in the major surface of the semiconductor substrate 1, is exposed, and a high concentration impurity diffusion layer 131 serving as a collector region after formation of the element is formed in the epiial growth layer 13. On the semiconductor substrate 1, a bipolar transistor element is formed.
Steps of forming the element will be described. First, refening to FIG. 1A, a p-type silicon substrate 2 containing boron (B) is formed on the major surface of the semiconductor substrate 1 by the nonselective epitaxial growth. The p-type silicon substrate 2 includes an intrinsic base region 2a formed on the element forming region by the epitaxial growth, and a p-type polycrystalline silicon region 2b formed on the element isolating region 10. Then, a silicon oxide film (SiO.sub.2) (not shown) is deposited on the silicon semiconductor layer 2 by the CVD (Chemical Vapor Deposition) method, and the anisotropic etching of the silicon oxide film is carnied out using a photoresist (not shown) as a mask to form an etching stopper 3 of an oxide film as shown in FIG. 1B(a). The etching stopper 3 occupies a plane region shown in FIG. 1B(b).
Then, as shown in FIG. 1C, a polyciysaine silicon layer 4 is deposited on the whole surface of the semiconductor substrate 1 so as to cover the silicon semiconductor layer 2 and the etching stopper 3, and boron ions are implanted into the polyciystalline silicon layer 4. Then, the silicon semiconductor layer 2, which has been formed by the non-selective epital growth, and the polycrystaline silicon film 4, into which boron ions have been implanted, are simultaneously patterned to form a base drawing electrode 41 and a collector drawing electrode 42 (not shown). Then, as shown in FIG. 1D, a silicon nitride film (Si.sub.3 N.sub.4) 5 is deposited on the semiconductor substrate 1 so as to cover the base drawing electrode 41 and collector drawing electrode 42, which have been allowed to remain after patterning, as well as the underlying polycrystalene silicon film 2. FIG. 1D(b) is a schematic plan view of the silicon nitride filMm 5 for covering the base drawing electrode 41, the collector drawing electrode 42 and the etching stopper 3.
Then, an opening 6 is formed in the base drawing electrode 41 and a portion of the silicon nitride film 5, which covers the base drawing electrode 41, by an anisotropic etching, such as the RIE (Reactive Ion Etching). At this time, the etching stopper 3 formed on the silicon semiconductor layer 2 is exposed to the bottom of the opening 6 as shown in FIG. 1E. Then, a silicon nitride film (not shown) is deposited on the whole surface of the semiconductor substrate 1, and a nitride film 7 is formed on the inner surface of the opening 6 by an anisotropic etching, such as the RIE. Then, as shown in FIG. 1F, the etching stopper 3 in the opening 6 is removed by etching with ammonium fluoride (NH.sub.4 F) solution to expose the surface of the semiconductor layer 2. Therefore, at this time, the etching stopper 3 is allowed to remain under the nitride film 7 formed on the side wall of the opening 6.
Then, a polycrystalline silicon film (not shown) is deposited on the whole surface of the silicon nitride film 5, and the ion implantation of arsenic (As) into the polycrystailline silicon film is carried out. Moreover, after a heating step, the arsenic in the polycrystalline silicon film is allowed to diffuse in the silicon semiconductor layer 2 to form an emitter region 9 in a portion in which the arsenic diffuses. Moreover, as shown in FIG. 1G, the polycrystalline silicon film is patterned by an anisotropic etching, such as the RIE, to form an emitter drawing electrode 8.
Then, an interlayer insulator film 14 of a silicon oxide film or the like is deposited on the emitter drawing electrode 8 and the silicon nitride film 5, and then, a contact hole is formed in the interlayer insulator film 14 to expose the emitter drawing electrode 8. Then, an emitter metal electrode 15 electrically connected to the exposed emitter drawing electrode 8 is formed of a metal, such as aluminum. At this time, contact holes are also formed in the silicon nitride film 5 and the base drawing electrode 41 and collector drawing electrode 42 of the interlayer insulator film 14 deposited thereon, and then, a base metal electrode 16 and a collector metal electrode 17, which are electrically connected to the base drawing electrode 41 and the collector drawing electrode 42, respectively, are formed of a metal, such as aluminum (see FIGS. 1H(a), (b) (c)).
In the above described conventional method for producing a semiconductor device, the polycrystalline silicon film serving as the base drawing electrode is partially removed by the anisotropic etching to form the emitter opening, so that it is required to form the silicon oxide film serving as the etching stopper 3. In addition, it is required to form doubling margins 23, 23 between the etching stopper 23 and the opening defining the emitter region 9 as shown in FIG. 1H(c).
However, although excessive base current flows through the base region 9 in the semiconductor layer 2 by the doubling margins 23, the semiconductor layer 2 of a mono-crystalline silicon has a higher value of resistance than that of the polycrystalline silicon film 4 for the base drawing electrode 41, so that the base resistance is tend to increase. There is a problem in that the increase of the base resistance causes the operation speed of the transistor element to decrease, so that noises increase when an analog operation is carried out.
In addition, the area of the element region is increased by the doubling margins 23, so that the base-to-collector capacity is tend to increase. There is a problem in that the increase of the base-to-collector capacity decrease the operation speed of the transistor element to increase electric power consumption.